Hardware Support for Efficient Packet Processing

Geib, Benjamin Ulrich

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URL: https://ub-madoc.bib.uni-mannheim.de/30849
URN: urn:nbn:de:bsz:180-madoc-308492
Document Type: Doctoral dissertation
Year of publication: 2012
Place of publication: Mannheim
Publishing house: Universität Mannheim
University: Universität Mannheim
Evaluator: Brüning, Ulrich
Date of oral examination: 21 March 2012
Publication language: English
Institution: School of Business Informatics and Mathematics > Rechnerarchitektur (Brüning -2008)
Subject: 004 Computer science, internet
Subject headings (SWD): Hardwareentwurf , Verbindungsstruktur , Hochleistungsrechnen
Keywords (English): Packet Processing , Low Latency , Tag Matching , Crossbar , Hardware Design , Interconnection Network , Computer Architecture , High Performance Computing
Abstract: Scalability is the key ingredient to further increase the performance of today’s supercomputers. As other approaches like frequency scaling reach their limits, parallelization is the only feasible way to further improve the performance. The time required for communication needs to be kept as small as possible to increase the scalability, in order to be able to further parallelize such systems. In the first part of this thesis ways to reduce the inflicted latency in packet based interconnection networks are analyzed and several new architectural solutions are proposed to solve these issues. These solutions have been tested and proven in a field programmable gate array (FPGA) environment. In addition, a hardware (HW) structure is presented that enables low latency packet processing for financial markets. The second part and the main contribution of this thesis is the newly designed crossbar architecture. It introduces a novel way to integrate the ability to multicast in a crossbar design. Furthermore, an efficient implementation of adaptive routing to reduce the congestion vulnerability in packet based interconnection networks is shown. The low latency of the design is demonstrated through simulation and its scalability is proven with synthesis results. The third part concentrates on the improvements and modifications made to EXTOLL, a high performance interconnection network specifically designed for low latency and high throughput applications. Contributions are modules enabling an efficient integration of multiple host interfaces as well as the integration of the on-chip interconnect. Additionally, some of the already existing functionality has been revised and improved to reach better performance and a lower latency. Micro-benchmark results are presented to underline the contribution of the made modifications.

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