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Efficient hardware for low latency applications
Leber, Christian
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thesis_christian_leber_print-1.pdf
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URL:
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https://ub-madoc.bib.uni-mannheim.de/32403
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URN:
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urn:nbn:de:bsz:180-madoc-324030
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Dokumenttyp:
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Dissertation
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Erscheinungsjahr:
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2012
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Ort der Veröffentlichung:
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Mannheim
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Verlag:
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Universität Mannheim
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Hochschule:
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Universität Mannheim
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Gutachter:
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Brüning, Ulrich
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Datum der mündl. Prüfung:
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20 August 2012
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Sprache der Veröffentlichung:
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Englisch
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Einrichtung:
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Fakultät für Wirtschaftsinformatik und Wirtschaftsmathematik > Rechnerarchitektur (Brüning 1996-2008)
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Fachgebiet:
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004 Informatik
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Normierte Schlagwörter (SWD):
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Hardwareentwurf , Speicherverwaltung , Mikroprogrammierung , Latenz , Kommunikationsprotokoll
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Freie Schlagwörter (Englisch):
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Computer Architecture , Low Latency , Micro Programming , Microcode Engine , Memory Management , Translation Lookaside Buffer , High Performance Computing , Remote Memory Access , Hardware Design , TCP/IP , Co-Simulation , Automatic Code Generation
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Abstract:
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The design and development of application specific hardware structures has a
high degree of complexity. Logic resources are nowadays often not the limit
anymore, but the development time.
The first part presents a generator which allows defining control and status
structures for hardware designs using an abstract high level language.
A novel method to inform host systems very efficiently about changes in the
register files is presented in the second part. It makes use of a microcode
programmable hardware unit.
In the third part a fully pipelined address translation mechanism for remote
memory access in HPC interconnection networks is presented, which features a new
concept to resolve dependency problems.
The last part of this thesis addresses the problem of sending TCP messages for a
low latency trading application using a hybrid TCP stack implementation that
consists of hardware and software components. Furthermore, a simulation
environment for the TCP stack is presented.
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