Efficient hardware for low latency applications

Leber, Christian

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URL: https://ub-madoc.bib.uni-mannheim.de/32403
URN: urn:nbn:de:bsz:180-madoc-324030
Document Type: Doctoral dissertation
Year of publication: 2012
Place of publication: Mannheim
Publishing house: Universität Mannheim
University: Universität Mannheim
Evaluator: Brüning, Ulrich
Date of oral examination: 20 August 2012
Publication language: English
Institution: School of Business Informatics and Mathematics > Rechnerarchitektur (Brüning -2008)
Subject: 004 Computer science, internet
Subject headings (SWD): Hardwareentwurf , Speicherverwaltung , Mikroprogrammierung , Latenz , Kommunikationsprotokoll
Keywords (English): Computer Architecture , Low Latency , Micro Programming , Microcode Engine , Memory Management , Translation Lookaside Buffer , High Performance Computing , Remote Memory Access , Hardware Design , TCP/IP , Co-Simulation , Automatic Code Generation
Abstract: The design and development of application specific hardware structures has a high degree of complexity. Logic resources are nowadays often not the limit anymore, but the development time. The first part presents a generator which allows defining control and status structures for hardware designs using an abstract high level language. A novel method to inform host systems very efficiently about changes in the register files is presented in the second part. It makes use of a microcode programmable hardware unit. In the third part a fully pipelined address translation mechanism for remote memory access in HPC interconnection networks is presented, which features a new concept to resolve dependency problems. The last part of this thesis addresses the problem of sending TCP messages for a low latency trading application using a hybrid TCP stack implementation that consists of hardware and software components. Furthermore, a simulation environment for the TCP stack is presented.

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