A Hardware Verification Methodology for an Interconnection Network with fast Process Synchronization


Burkhardt, Niels


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URL: https://ub-madoc.bib.uni-mannheim.de/33110
URN: urn:nbn:de:bsz:180-madoc-331107
Dokumenttyp: Dissertation
Erscheinungsjahr: 2012
Ort der Veröffentlichung: Mannheim
Verlag: Universität Mannheim
Hochschule: Universität Mannheim
Gutachter: Brüning, Ulrich
Datum der mündl. Prüfung: 19 März 2013
Sprache der Veröffentlichung: Englisch
Einrichtung: Fakultät für Wirtschaftsinformatik und Wirtschaftsmathematik > Rechnerarchitektur (Brüning 1996-2008)
Fachgebiet: 004 Informatik
Normierte Schlagwörter (SWD): Hardwareentwurf , Verbindungsnetzwerk , Kommunikationsprotokoll , Verifikation
Freie Schlagwörter (Englisch): Hardware Design , Interconnection Network , Network Protocol , Functional Verification
Abstract: Shrinking process node sizes allow the integration of more and more functionality into a single chip design. At the same time, the mask costs to manufacture a new chip increases steadily. For the industry this cost increase can be absorbed by selling more chips. Furthermore, new innovative chip designs have a higher risk. Therefore, the industry only changes small parts of a chip design between different generations to minimize their risks. Thus, new innovative chip designs can only be realized by research institutes, which do not have the cost restrictions and the pressure from the markets as the industry. Such an innovative research project is EXTOLL, which is developed by the Computer Architecture Group of the University of Heidelberg. It is a new interconnection network for High performance Computing, and targets the problems of existing interconnection networks commercially available. EXTOLL is optimized for a high bandwidth, a low latency, and a high message rate. Especially, the low latency and high message rate become more important for modern interconnection networks. As the size of networks grow, the same computational problem is distributed to more nodes. This leads to a lower data granularity and more smaller messages, that have to be transported by the interconnection network. The problem of smaller messages in the interconnection network is addressed by this thesis. It develops a new network protocol, which is optimized for small messages. It reduces the protocol overhead required for sending small messages. Furthermore, the growing network sizes introduce a reliability problem. This is also addressed by the developed efficient network protocol. The smaller data granularity also increases the need for an efficient barrier synchronization. Such a hardware barrier synchronization is developed by thesis, using a new approach of integrating the barrier functionality into the interconnection network. The masks costs to manufacture an ASIC make it difficult for a research institute to build an ASIC. A research institute cannot afford re-spin, because of the costs. Therefore, there is the pressure to make it right the first time. An approach to avoid a re-spin is the functional verification in prior to the submission. A complete and comprehensive verification methodology is developed for the EXTOLL interconnection network. Due to the structured approach, it is possible to realize the functional verification with limited resources in a small time frame. Additionally, the developed verification methodology is able to support different target technologies for the design with a very little overhead.




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